Description
As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
Preferred Qualifications
The ideal candidate will have deep design experience in high PHY and/or SOC designs. Deep Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floor-planning, and Place & Route. Experience in developing and implementing Power-grid and Clock specifications. Strong understanding of all aspects of Physical construction, Integration and Physical Verification. Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard Physical Design & Synthesis tools. Deep Understanding of scripting languages such as Perl/Tcl, solid understanding of Extraction and STA methodology and tools. Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
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