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Description
As a CPU Implementation Engineer you will drive or participate in the following - Will work extensively with micro-architects to define the micro-architecture, perform design feasibility and do power, performance, and area (PPA) trade-offs - Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis and place-and-route tools targeting ambitious goals for PPA - Will be responsible for block-level design delivery along with closure of backend flows, electrical requirements and improving silicon yield - Will work closely with internal CAD and PD methodology teams on industry standard synthesis/PNR tool features and optimizations and their adoption in CPU design - Will work with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability - Will work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA
Minimum Qualifications
- BS EE/CE or equivalent experience. - Be an outstanding teammate with excellent communication skills and the desire to address diverse challenges.
Preferred Qualifications
Solid electrical engineering fundamentals in logic design and digital circuits Basic knowledge of CPU pipeline, and physical design concepts related to timing and power Basic knowledge of scripting/programming acquired during coursework, internship or industry work Ability to work well in a team, self-motivated and excellent communication skills
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