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Senior Physical Design Engineer

EnCharge AI
Posted a month ago, valid for 2 days
Location

Santa Clara, CA, US

Salary

Competitive

Contract type

Full Time

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Sonic Summary

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  • EnCharge AI is seeking a Senior Physical Design Engineer with over 10 years of experience in physical design, specifically in chip-level implementation.
  • The ideal candidate should have deep expertise in physical design, timing closure, and low-power design, along with hands-on experience using Cadence EDA tools.
  • Proficiency in low-power design concepts, EM/IR checks, and debugging is necessary, as well as strong scripting skills in TCL or Python for automation.
  • Experience with both top-level and block-level physical design is required, and familiarity with hierarchical floorplanning and physical design methodology is preferred.
  • The salary for this position is competitive, reflecting the candidate's extensive experience and expertise in the field.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

About the Role

We are seeking a highly experienced Senior Physical Design Engineer with a strong background in chip-level implementation and EDA tools. The ideal candidate will have deep expertise in physical design, timing closure, and low-power design.

Qualifications

  • 10+ years of experience in physical design (excluding other areas such as logic design or CAD).

  • Strong understanding of EDA implementation for chip design, with hands-on experience in Cadence tools (must-have).

  • Strong knowledge of timing concepts and timing closure techniques for chip design.

  • Experience with both top-level and block-level physical design is required; experience with hierarchical floorplanning is a plus.

  • Proficiency in low-power design concepts and debugging is necessary.

  • Experience with EM/IR checks, debugging, and issue resolution, including power grid verification, is required.

  • Strong scripting skills in TCL or Python for automation are important.

  • Understanding of process concepts is needed for physical verification as part of routing tasks.

  • Experience with physical design methodology and flow setup is preferred; this role will involve advanced flow evaluations.

  • Additional experience in areas such as PDK management or foundry tapeout processes is a plus,

 




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By applying, a EnCharge AI account will be created for you. EnCharge AI's Privacy Policy and Terms & Conditions will apply.

SonicJobs' Terms & Conditions and Privacy Policy also apply.